Semiconductor device package and method of manufacturing the same

ABSTRACT

A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a package body and a shield. The substrate has a first surface and a second surface opposite to the first surface. The substrate defines a cavity from the second surface extending into the substrate. The first electronic component is disposed on the first surface of the substrate. The second electronic component is disposed within the cavity of the substrate. The package body is disposed on a portion of the first surface of the substrate and covers the first electronic component. The shield is disposed on external surfaces of the package body.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No. 16/388,834 filed Apr. 18, 2019, the contents of which is incorporated herein by reference in its entirety.

BACKGROUND 1. Technical Field

The present disclosure relates to a semiconductor device package and a method of manufacturing the same.

2. Description of the Related Art

A semiconductor package device may include multiple electronic components to increase its performance and functionality. To reduce the area or footprint of a semiconductor package device, electronic components may be mounted to both a top surface and a bottom surface of a substrate. The electronic components can be arranged side-by-side on the top surface or the bottom surface of the substrate. However, this will increase the area of semiconductor device package. The electronic components may be arranged in a stacking arrangement. However, this will increase the thickness of the semiconductor device package, which will in turn hinder the semiconductor device package from being connected to another circuit board.

SUMMARY

In accordance with some embodiments of the present disclosure, a semiconductor device package includes a substrate, a first electronic component, a second electronic component, a package body and a shield. The substrate has a first surface and a second surface opposite to the first surface. The substrate defines a cavity from the second surface extending into the substrate. The first electronic component is disposed on the first surface of the substrate. The second electronic component is disposed within the cavity of the substrate. The package body is disposed on a portion of the first surface of the substrate and covers the first electronic component. The shield is disposed on external surfaces of the package body.

In accordance with some embodiments of the present disclosure, a semiconductor device package includes a first substrate, a first electronic component, a second electronic component, a frame board, a package body and a shield. The first substrate has a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface of the first substrate. The second electronic component is disposed on the second surface of the first substrate. The frame board is disposed on the second surface of the first substrate and surrounds the second electronic component. The package body is disposed on a portion of the first surface of the first substrate and covers the first electronic component. The shield is disposed on external surfaces of the package body.

In accordance with some embodiments of the present disclosure, a method of manufacturing an optical module includes (a) providing a first substrate having a first surface and a second surface opposite to the first surface; (b) disposing a first electronic component on the first surface of the first substrate; (c) disposing a frame board on the first surface of the first substrate to surround the first electronic component, the frame board having conductive vias penetrating the frame board and electrically connected to the first substrate; and (d) connecting a second electronic component on the second surface of the first substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates a cross-sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure.

FIG. 1B illustrates an enlarged view of a heat dissipation element in accordance with some embodiments of the present disclosure.

FIG. 2A illustrates a cross-sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure.

FIG. 2B illustrates a cross-sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure.

FIG. 3 illustrates a cross-sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure.

FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E, FIG. 4F, FIG. 4G and FIG. 4H illustrate a semiconductor manufacturing method in accordance with some embodiments of the present disclosure.

FIG. 5A, FIG. 5B, FIG. 5C and FIG. 5D illustrate a semiconductor manufacturing method in accordance with some embodiments of the present disclosure.

FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D and FIG. 6E illustrate a semiconductor manufacturing method in accordance with some embodiments of the present disclosure.

FIG. 7A and FIG. 7B illustrate a semiconductor manufacturing method in accordance with some embodiments of the present disclosure.

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. The present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION

FIG. 1A illustrates a cross-sectional view of a semiconductor device package 1 in accordance with some embodiments of the present disclosure. The semiconductor device package 1 includes a substrate 10, electronic components 11 a, 11 b, 14 a, 14 b, a package body 12, a shield 13 and electrical contacts 15.

The substrate 10 may be, for example, a printed circuit board (PCB), such as a paper-based copper foil laminate, a composite copper foil laminate, a polymer-impregnated glass-fiber-based copper foil laminate, or a combination of two or more thereof. The substrate 10 may include an interconnection structure, such as a redistribution layer (RDL). In some embodiments, the substrate 10 is or includes a multi-layer substrate. The substrate 10 has a surface 101, a surface 102 opposite to the surface 101 and a lateral surface 103 extending between the surface 101 and the surface 102. The substrate 10 defines a cavity 11 c from the surface 102 into the substrate 10.

The electronic components 11 a and 11 b are disposed on the surface 101 of the substrate 10. The electronic components 11 a may be an active component or another semiconductor device, such as an integrated circuit (IC) chip or a die. In some embodiments, the electronic components 11 a could be any active component or another semiconductor package device. The electronic components 11 b may be passive components, such as capacitors, resistors or inductors. The electronic components 11 a and 11 b may be electrically connected to one or more of another electronic component and/or the substrate 10 (e.g., to the interconnection layer), and electrical connection may be attained by way of flip-chip, wire-bond techniques or surface mount technology (SMT).

The package body 12 is disposed on the surface 101 of the substrate 10. In some embodiments, the package body 12 is disposed on a portion of the surface of the substrate 10 and covers the electronic components 11 a and 11 b. In some embodiments, the package body 12 includes an epoxy resin including fillers, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material including a silicone dispersed therein, or a combination thereof.

The shield 13 is disposed on external surfaces of the package body 12 (e.g., a top surface and lateral surfaces) and covers the package body 12 and electrical components 11 a, 11 b. In some embodiments, the shield 13 covers at least a portion of the lateral surface 103 of the substrate 10. The shield 13 is electrically connected to grounding elements of the substrate 10. In some embodiments, the shield 13 is a conductive thin film, and may include, for example, aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni) or stainless steel, or a mixture, an alloy, or other combination thereof. The shield 13 may include a single conductive layer or multiple conductive layers. In some embodiments, the shield 13 includes multiple conductive layers, and the multiple conductive layers may include a same material, or ones of the multiple conductive layers may include different materials, or each of the multiple conductive layers may include different materials from others of the multiple conductive layers. The shield 13 can prevent the electronic components 11 a, 11 b from electromagnetic interference (EMI).

The electronic components 14 a and 14 b are disposed within the cavity 14 c of the substrate 10. The electronic components 14 a may be an active component, such as an IC chip or a die. In some embodiments, the electronic component 14 a is a system-on-a-chip (SoC), which may include one or more processors, controllers or any other suitable electronic devices. The electronic component 14 b may be a passive component, such as a capacitor, a resistor or an inductor. The electronic components 14 a and 14 b may be electrically connected to one or more of another electronic component and/or the substrate 10 (e.g., to the interconnection layer), and electrical connection may be attained by way of flip-chip or wire-bond techniques or SMT. In some embodiments, an underfill 14u may be disposed between an active surface of the electronic component 14 a and the substrate 10. In some embodiments, a portion of the electronic components 14 a and 14 b may be exposed from the surface 102 of the substrate 10. For example, a thickness of the electronic component 14 a or 14 b is greater than a depth of the cavity 11 c. In other embodiments, the thickness of the electronic component 14 a or 14 b is equal to or less than the depth of the cavity 11 c.

In some embodiments, a heat dissipation element 14 h may be disposed on a backside surface of the active component (e.g., the electronic component 14 a). In some embodiments, the heat dissipation element 14 h includes may include, but is not limited to, graphite, graphene, a carbon fiber, a boron nitride or the like. In other embodiments, the heat dissipation element 14 h may include a structure as shown in FIG. 1B, which illustrates an enlarged portion of a portion of the semiconductor device package 1 encircled by a dotted line A. As shown in FIG. 1B, a graphite film 14 h 1 is disposed on the backside surface of the electronic component 14 a, and a conductive layer 14 h 2 is disposed on the graphite film to further improve the heat dissipation. In some embodiments, the heat dissipation element 14 h can be omitted depending on different design specifications.

The electrical contacts 15 are disposed on the surface 102 of the substrate 10 and may be electrically connected to the substrate 10. In some embodiments, the electrical contacts 15 are Controlled Collapse Chip Connection (C4) bumps, solder bumps, one or more Land Grid Arrays (LGA), or a combination of two or more thereof.

In accordance with the embodiments as shown in FIG. 1A, since the electronic components 14 a and 14 b are disposed within the cavity 11 c defined by the substrate 10, the thickness of the semiconductor device package 1 can be reduced. In addition, a distance between the electronic component 14 a or 14 b and a bottom portion of the electrical contacts (or a distance between the electronic component 14 a or 14 b and a circuit board on which the semiconductor device package 1 is bonded) increases, which can prevent the electronic components 14 a and 14 b from being damaged. Furthermore, it is flexible to select the size of the electrical contacts 15.

FIG. 2A illustrates a cross-sectional view of a semiconductor device package 2 in accordance with some embodiments of the present disclosure. The semiconductor device package 2 is similar to the semiconductor device package 1 in FIG. 1A, and the differences therebetween are described blow.

A frame board 20 (or interposer) is disposed on the surface 102 of the substrate 10. In some embodiments, the shield 13 is disposed on the lateral surface 103 of the substrate 10 and at least a portion of the lateral surface of the frame board 20. The frame board 20 has an opening 20 c to accommodate the electronic components 14 a and 14 b, which are disposed on the surface 102 of the substrate 10. The frame board 20 surrounds the electronic components 14 a and 14 b. The frame board 20 may include at least one via 20 v penetrating the frame board 20 and electrically connecting the substrate 10 to the electrical contacts 15. In some embodiments, the frame board 20 is electrically connected to the substrate 10 through an adhesive element 20 p (e.g., pre-solder). The frame board 20 and the electrical contacts 15 may be arranged in or near the periphery of surface 102 of the substrate 10. The frame board 20 may include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate.

In accordance with the embodiments as shown in FIG. 2A, since the electronic components 14 a and 14 b are disposed within the cavity defined by the frame board 20, a distance between the electronic component 14 a or 14 b and a bottom portion of the electrical contacts (or a distance between the electronic component 14 a or 14 b and a circuit board on which the semiconductor device package 2 is bonded) increases, which can prevent the electronic components 14 a and 14 b from being damaged. Furthermore, it is flexible to select the size of the electrical contacts 15.

FIG. 2B illustrates a cross-sectional view of a semiconductor device package 2′ in accordance with some embodiments of the present disclosure. The semiconductor device package 2′ is similar to the semiconductor device package 2 in FIG. 2A except that the semiconductor device package 2′ further includes a package body 22 disposed within the cavity 20 c to cover the electronic components 14 a and 14 b.

FIG. 3 illustrates a cross-sectional view of a semiconductor device package 2 in accordance with some embodiments of the present disclosure. The semiconductor device package 3 is similar to the semiconductor device package 1 in FIG. 1, and the differences therebetween are described blow.

A substrate 30 is disposed on the surface 102 of the substrate 10. The substrate 30 may be, for example, a PCB, such as a paper-based copper foil laminate, a composite copper foil laminate, a polymer-impregnated glass-fiber-based copper foil laminate, or a combination of two or more thereof. The substrate 30 may include an interconnection structure, such as a RDL. In some embodiments, the substrate 30 is or includes a multi-layer substrate. In some embodiments, the number of the layers of the substrate 30 can be the same as, greater than or less than the number of the layers of the substrate 10 depending on different design specifications. The substrate 30 has a surface 301 facing the substrate 10 and a surface 302 opposite to the surface 301. The substrate 30 may be electrically connected to the substrate 10 through the adhesive element 20 p (e.g., pre-solder)

A frame board 31 (or interposer) is disposed on the surface 302 of the substrate 30. The frame board 31 has an opening 31 c to accommodate the electronic components 14 a and 14 b, which are disposed on the surface 302 of the substrate 30. The frame board 31 surrounds the electronic components 14 a and 14 b. The frame board 31 is arranged in or near the periphery of surface 302 of the substrate 30. The frame board 31 may include at least one via 31 v penetrating the frame board 31 and electrically connected to the substrate 30. In some embodiments, the frame board 31 is electrically connected to the substrate 30 through the adhesive element 20 p (e.g., pre-solder). The frame board 31 may include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate.

In accordance with the embodiments as shown in FIG. 3, since the electronic components 14 a and 14 b are disposed within the cavity defined by the frame board 31, a distance between the electronic component 14 a or 14 b and a bottom portion of the electrical contacts (or a distance between the electronic component 14 a or 14 b and a circuit board on which the semiconductor device package 2 is bonded) increases, which can prevent the electronic components 14 a and 14 b from being damaged. Furthermore, it is flexible to select the size of the electrical contacts 15.

FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E, FIG. 4F, FIG. 4G and FIG. 4H illustrate a semiconductor manufacturing method in accordance with some embodiments of the present disclosure. In some embodiments, the method in FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E, FIG. 4F, FIG. 4G and FIG. 4H can be used to manufacture the semiconductor device package 2 in FIG. 2.

Referring to FIG. 4A, a strip of substrates including the substrate 10 is provided, and solder paste printing is performed on a surface 102 of the substrate 10. Referring to FIG. 4B, electronic components 14 b are disposed on the surface 102 of the substrate 10 by, for example, side mount technology (SMT). Referring to FIG. 4C, an electronic component 14 a is bonded to the surface 102 of the substrate 10. Then, an underfill 14u may be formed between the active surface of the electronic component 14 a and the surface 102 of the substrate 10 as shown in FIG. 4D. In some embodiments, a strip test (e.g., active temperature control, ATC) may be carried out.

Referring to FIG. 4E, a frame board 20 with vias 20 v penetrating the frame board 20 is disposed on the surface 102 of the substrate 10 to surround the electronic components 14 a and 14 b. In some embodiments, the frame board 20 is disposed on the surface 102 of the substrate 10 by, for example, lamination. Then, the reflow and press operations may be carried out to bond the frame board 20 to the substrate 10. Referring to FIG. 4F, solder paste printing is performed on a surface 101 of the substrate 10, and then electronic components 11 a and 11 b are disposed on the surface 101 of the substrate 10 by, for example, SMT.

Referring to FIG. 4G, a package body 12 is formed on a portion of the surface 101 of the substrate 10 to cover or encapsulate the electronic components 11 a and 11 b. In some embodiments, the package body 12 is formed by, for example, molding technique (e.g., selective molding). Then, a singulation is performed to separate the substrate strips including the substrate 10. In some embodiments, after singulation, a lateral surface of the package body 12 is recessed from a lateral surface of the individual substrate 10.

Referring to FIG. 4H, a shield 13 is formed on the external surfaces of the package body 12. In some embodiments, the shield 13 may be also formed on the lateral surface of the substrate 10 and a portion of the lateral surface of the frame board 20. In some embodiments, the shield 13 is formed by, for example, sputtering (e.g., selective sputtering). Electrical contacts 15 are then formed on the vias 20 v exposed from the frame board 20 to form the semiconductor device package as shown in FIG. 2. In some embodiments, a test (e.g., open/short test) may be carried out on the individual semiconductor device package 2.

FIG. 5A, FIG. 5B, FIG. 5C and FIG. 5D illustrate a semiconductor manufacturing method in accordance with some embodiments of the present disclosure. In some embodiments, the method in FIG. 5A, FIG. 5B, FIG. 5C and FIG. 5D can be used to manufacture a portion of the semiconductor device package 3 in FIG. 3 (e.g., including the substrate 10 and the structure above the structure 10).

Referring to FIG. 5A, a strip of substrates including a substrate 10 is provided, and solder paste printing is performed on a surface 101 of the substrate 10. Referring to FIG. 5B, electronic components 11 a and 11 b are disposed on the surface 101 of the substrate 10 by, for example, SMT.

Referring to FIG. 5C, a package body 12 is formed on a portion of the surface 101 of the substrate 10 to cover or encapsulate the electronic components 11 a and 11 b. In some embodiments, the package body 12 is formed by, for example, molding technique (e.g., selective molding). Then, a singulation is performed to separate the substrate strips including the substrate 10. In some embodiments, after singulation, a lateral surface of the package body 12 is recessed from a lateral surface of the individual substrate 10.

Referring to FIG. 5D, a shield 13 is formed on the external surfaces of the package body 12. In some embodiments, the shield 13 may be also formed on at least a portion of the lateral surface of the substrate 10. In some embodiments, the shield 13 is formed by, for example, sputtering (e.g., selective sputtering). In some embodiments, a test (e.g., open/short test) may be carried out on the individual structure as shown in FIG. 5D.

FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D and FIG. 6E illustrate a semiconductor manufacturing method in accordance with some embodiments of the present disclosure. In some embodiments, the method in FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D and FIG. 6E can be used to manufacture a portion of the semiconductor device package 3 in FIG. 3 (e.g., including the substrate 30 and the structure below the substrate 30).

Referring to FIG. 6A, a strip of substrates including the substrate 30 is provided, and solder paste printing is performed on a surface 302 of the substrate 30. Referring to FIG. 6B, electronic components 14 b are disposed on the surface 302 of the substrate 30 by, for example, side mount technology (SMT). Referring to FIG. 6C, an electronic component 14 a is bonded to the surface 302 of the substrate 30. Then, an underfill 14u may be formed between the active surface of the electronic component 14 a and the surface 302 of the substrate 30 as shown in FIG. 6D.

Referring to FIG. 6E, a frame board 31 with vias 31 v penetrating the frame board 31 is disposed on the surface 302 of the substrate 30 to surround the electronic components 14 a and 14 b. In some embodiments, the frame board 31 is disposed on the surface 302 of the substrate 30 by, for example, lamination. Then, the reflow and press operations may be carried out to bond the frame board 31 to the substrate 30. Then, a singulation is performed to separate the substrate strips including the substrate 30. In some embodiments, a unit test (e.g., ATC) may be carried out on the individual structure as shown in FIG. 6E.

FIGS. 7A and 7B illustrate a semiconductor manufacturing method in accordance with some embodiments of the present disclosure. In some embodiments, the method in FIGS. 7A and 7B can be used to manufacture the semiconductor device package 3 in FIG. 3.

Referring to FIG. 7A, the structure as shown in FIG. 5D is provided, and solder paste printing is performed on a surface 102 of the substrate 10 to form solder pastes 10 s.

Referring to FIG. 7B, the structure as shown in FIG. 6E is disposed on the surface 102 of the substrate 10. In some embodiments, the structure as shown in FIG. 6E is disposed on the surface 102 of the substrate 10 by, for example, lamination. Then, the reflow and press operations may be carried out to bond the structure as shown in FIG. 6E to the substrate 10 to form the semiconductor device package 3 as shown in FIG. 3.

In accordance with the embodiments as shown in FIGS. 4A-4H, the strip test is performed to the electronic components 14 a, 14 b disposed on one surface (e.g., surface 102) of the strip of the substrates, and then a singulation is performed after the electronic components 11 a, 11 b are connected to the other surface (e.g., surface 101) of the strip of substrates. Therefore, even if some of the electronic components 14 a, 14 b do not pass the strip test, the electronic component 11 a, 11 b will be still disposed on the unit of the substrate on which those defective electronic components 14 a, 14 b are disposed, which will decrease the yield rate of the semiconductor device package and increase the manufacturing cost. In addition, the open/short test is carried out to the electronic components 11 a, 11 b after all the electronic components 11 a, 11 b, 14 a and 14 b are connected to the both surfaces of the substrate 10. Therefore, if the electronic components 11 a, 11 b do not pass the test, the entire device package fails regardless whether the electronic components 14 a, 14 b pass the strip test as mentioned above, which will decrease the yield rate of the semiconductor device package and increase the manufacturing cost.

As shown in FIGS. 5A-5D, the open/short test is performed to the electronic components 11 a, 11 b disposed on the individual substrate 10 after singulation process. As shown in FIGS. 6A-6E, the unit test is performed to the electronic components 14 a, 14 b disposed on the individual substrate 30 after singulation process. As shown in FIGS. 7A and 7B, the structure shown in FIG. 5D, which passes the open/short test, and the structure shown in FIG. 6E, which passes the unit test, are connected to form the semiconductor device package 3. This can increase the yield rate of the semiconductor device package and reduce the manufacturing cost.

As used herein, the terms “substantially,” “substantial,” “approximately,” and “about” are used to denote and account for small variations. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, a thickness of a film or a layer being “substantially uniform” can refer to a standard deviation of less than or equal to ±10% of an average thickness of the film or the layer, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane. Two surfaces or components can be deemed to be “substantially perpendicular” if an angle therebetween is, for example, 90°±10°, such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°. When used in conjunction with an event or circumstance, the terms “substantially,” “substantial,” “approximately,” and “about” can refer to instances in which the event or circumstance occurs precisely, as well as instances in which the event or circumstance occurs to a close approximation.

As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

As used herein, the terms “conductive,” “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically indicate those materials that exhibit little or no opposition to the flow of an electric current. One measure of electrical conductivity is Siemens per meter (S/m). Typically, an electrically conductive material is one having a conductivity greater than approximately 10⁴ S/m, such as at least 10⁵ S/m or at least 10⁶ S/m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It can be understood that such range formats are used for convenience and brevity, and should be understood flexibly to include not only numerical values explicitly specified as limits of a range, but also all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the present disclosure. It can be clearly understood by those skilled in the art that various changes may be made, and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus, due to variables in manufacturing processes and such. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it can be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure. 

What is claimed is:
 1. A semiconductor device package, comprising: a substrate having a first surface and a second surface opposite to the first surface; a first electronic component disposed on the first surface of the substrate; a second electronic component disposed on the second surface of the substrate; an interposer disposed on the second surface of the substrate; a conductive element electrically connecting the interposer to the substrate; and a first package body disposed on the first surface of the substrate and covering the first electronic component, wherein the first package body exposes a portion of the first surface of the substrate.
 2. The semiconductor device package of claim 1, further comprising a shield disposed on the first package body and exposing the portion of the first surface of the substrate.
 3. The semiconductor device package of claim 2, wherein the shield exposes a portion of a lateral surface of the substrate.
 4. The semiconductor device package of claim 2, wherein the shield exposes a portion of the interposer.
 5. The semiconductor device package of claim 4, wherein the shield exposes at least two lateral surface of the interposer.
 6. The semiconductor device package of claim 1, wherein a lateral surface of the interposer is substantially aligned with a lateral surface of the substrate.
 7. The semiconductor device package of claim 1, further comprising a second package body covering the second electronic component.
 8. The semiconductor device package of claim 1, wherein the portion of the first surface of the substrate overlaps at least a portion of the interposer.
 9. The semiconductor device package of claim 1, wherein the portion of the first surface of the substrate extends to an edge of a lateral surface of the substrate.
 10. A semiconductor device package, comprising: a substrate having a first surface and a second surface opposite to the first surface; a first electronic component disposed on the first surface of the substrate; a second electronic component disposed on the second surface of the substrate; an interposer disposed on the second surface of the substrate; a first package body disposed on the first surface of the substrate and covering the first electronic component, the first package body exposing a portion of the first surface of the substrate; and a second package body covering the second electronic component.
 11. The semiconductor device package of claim 10, wherein the portion of the first surface of the substrate extends to an edge of a lateral surface of the substrate.
 12. The semiconductor device package of claim 10, wherein the portion of the first surface of the substrate overlaps at least a portion of the interposer.
 13. The semiconductor device package of claim 10, wherein second package body overlaps the portion of the first surface of the substrate.
 14. The semiconductor device package of claim 10, wherein a first lateral surface of the first package body is non-coplanar with a first lateral surface of the substrate.
 15. The semiconductor device package of claim 14, wherein a second lateral surface of the first package body is non-coplanar with a second lateral surface of the substrate.
 16. The semiconductor device package of claim 15, further comprising a shield disposed on the first lateral surface and the second lateral surface of the first package body.
 17. A semiconductor device package, comprising: a substrate having a first surface and a second surface opposite to the first surface; an interposer adjacent to the first surface of the substrate and configured to electrically connect an external device to the substrate; and a package body adjacent to the first surface of the substrate and exposing a portion of the first surface of the substrate.
 18. The semiconductor device package of claim 17, wherein the portion of the first surface of the substrate extends to an edge of a lateral surface of the substrate.
 19. The semiconductor device package of claim 17, wherein the portion of the first surface of the substrate overlaps at least a portion of the interposer.
 20. The semiconductor device package of claim 17, further comprising a shield disposed on the package body and exposing the portion of the first surface of the substrate. 